1. Field of the Invention
The invention relates to a timing generating apparatus, more particularly to a timing generating apparatus with self-calibrating capability.
2. Description of the Related Art
A timing generator is generally used to provide a timing pulse signal to an IC automatic test equipment (ATE) such that modules of the IC ATE can operate according to the timing pulse signal. Since IC ATE needs to test various IC products, the timing generator must provide accurate timing pulses to conform with a wide range of IC products. Recently, CMOS components are used in the IC ATE. However, due to changes in temperature, CMOS components will experience timing variation such that a compensation or calibration circuit is needed.
Referring to FIG. 1, a conventional timing generating apparatus is shown to include a master timing module 10, and a plurality of slave timing modules 11, each of which is coupled electrically to the master timing module 10. The master timing module 10 receives an external reference clock, and generates a plurality of coarse timing pulse signals. Each of the slave timing modules 11 receives the coarse timing pulse signals, and is operable so as to generate a fine timing pulse signal according to a selected one of the coarse timing pulse signals. For example, the coarse timing pulse signals have different time periods, such as 1.0 ns, 2.0 ns, 3.0 ns, . . . . The slave timing modules can generate a plurality of timing pulse signals with different adjustments in time periods, such as 0.05 ns, 0.10 ns, 0.15 ns, . . . . When the conventional timing generating apparatus needs to generate a timing pulse signal with a time period of 6.12 ns, the coarse timing pulse signal with a time period of 6.0 ns is selected by one of the slave timing modules 11 that generates a phase delay of 0.12 ns.
FIG. 2 illustrates an embodiment of the conventional timing generating apparatus. The master timing module 10 is a phase locked ring oscillator that is a closed-loop system. The slave timing module 11 is composed of a programmable delay unit that is an open-loop system and that is unable to maintain the accuracy of the fine timing pulse signal.
FIG. 3 illustrates another embodiment of the conventional timing generating apparatus. In FIG. 3, unlike the embodiment of FIG. 2, the slave timing module 11' is implemented as a phase locked delay line for generating the fine timing pulse signal from the coarse timing pulse signal via a phase selection multiplexer 111. While the fine timing pulse signal can be obtained from the slave timing module 11', it is noted that the phase selection multiplexer 111 and drivers are outside of a phase locked loop of the phase locked delay line. Therefore, the accuracy of the fine timing pulse signal is affected by the high temperature coefficient of solid state devices such that a temperature compensation mechanism is needed to maintain the accuracy of the fine timing pulse signal at different temperatures.